CFS=Val_0x0, FRF=Val_0x0, TMOD=Val_0x0, SCPH=Val_0x0, SSTE=Val_0x0, SCPOL=Val_0x0, SPI_IS_MST=Val_0x0, SLV_OE=Val_0x0, SRL=Val_0x0
Control Register 0
| DFS | Data Frame Size. Selects the data frame length. When the data frame size is programmed to be less than 32 bits, the receive data is automatically right-justified by the receive logic, with the upper bits of the receive FIFO zero-padded. User must right-justify transmit data before writing into the transmit FIFO. The transmit logic ignores the upper unused bits when transmitting the data. 3 (Val_0x3): 04-bit serial data transfer 4 (Val_0x4): 05-bit serial data transfer 5 (Val_0x5): 06-bit serial data transfer 6 (Val_0x6): 07-bit serial data transfer 7 (Val_0x7): 08-bit serial data transfer 8 (Val_0x8): 09-bit serial data transfer 9 (Val_0x9): 10-bit serial data transfer 10 (Val_0xA): 11-bit serial data transfer 11 (Val_0xB): 12-bit serial data transfer 12 (Val_0xC): 13-bit serial data transfer 13 (Val_0xD): 14-bit serial data transfer 14 (Val_0xE): 15-bit serial data transfer 15 (Val_0xF): 16-bit serial data transfer 16 (Val_0x10): 17-bit serial data transfer 17 (Val_0x11): 18-bit serial data transfer 18 (Val_0x12): 19-bit serial data transfer 19 (Val_0x13): 20-bit serial data transfer 20 (Val_0x14): 21-bit serial data transfer 21 (Val_0x15): 22-bit serial data transfer 22 (Val_0x16): 23-bit serial data transfer 23 (Val_0x17): 24-bit serial data transfer 24 (Val_0x18): 25-bit serial data transfer 25 (Val_0x19): 26-bit serial data transfer 26 (Val_0x1A): 27-bit serial data transfer 27 (Val_0x1B): 28-bit serial data transfer 28 (Val_0x1C): 29-bit serial data transfer 29 (Val_0x1D): 30-bit serial data transfer 30 (Val_0x1E): 31-bit serial data transfer 31 (Val_0x1F): 32-bit serial data transfer |
| FRF | Frame Format. Selects which serial protocol transfers the data. 0 (Val_0x0): Motorola SPI frame format 1 (Val_0x1): Texas Instruments SSP frame format 2 (Val_0x2): National Semiconductors Microwire frame format |
| SCPH | Serial Clock Phase. Valid when the FRF bit is set to Motorola SPI. The serial clock phase selects the relationship of the serial clock with the slave select signal. When SCPH = 0, data are captured on the first edge of the serial clock. When SCPH = 1, the serial clock starts toggling one cycle after the slave select line is activated, and data are captured on the second edge of the serial clock. 0 (Val_0x0): Serial clock toggles in middle of first bit 1 (Val_0x1): Serial clock toggles at start of first bit |
| SCPOL | Serial Clock Polarity. Valid when the Frame Format (FRF) bit is set to Motorola SPI. Used to select the polarity of the inactive serial clock, which is held inactive when the SPI master is not actively transferring data on the serial bus. 0 (Val_0x0): Inactive state of serial clock is low 1 (Val_0x1): Inactive state of serial clock is high |
| TMOD | Transfer Mode. Selects the mode of transfer for serial communication. This field does not affect the transfer duplicity. Only indicates whether the receive or transmit data are valid. In Transmit Only mode, data received from the external device is not valid and is not stored in the receive FIFO memory; it is overwritten on the next transfer. In Receive Only mode, transmitted data are not valid. After the first write to the transmit FIFO, the same word is retransmitted for the duration of the transfer. In Transmit and Receive mode, both transmit and receive data are valid. The transfer continues until the transmit FIFO is empty. Data received from the external device are stored into the receive FIFO memory, where it can be accessed by the host processor. 0 (Val_0x0): Transmit and Receive 1 (Val_0x1): Transmit Only mode 2 (Val_0x2): Receive Only mode 3 (Val_0x3): EEPROM Read mode |
| SLV_OE | Slave Output Enable. Relevant only when the SPI is configured as a serial slave device. When configured as a serial master, this bit has no functionality. This bit enables or disables the setting of the output enable signal from the SPI serial slave. When the SLV_OE = 0x1, the output enable signal can never be active. When the output enable signal controls the tri-state buffer on the TXD output from the slave, a high impedance state is always present on the slave TXD output when the SLV_OE bit is set to 0x1. This is useful when the master transmits in broadcast mode (master transmits data to all slave devices). Only one slave may respond with data on the master RXD line. This bit is enabled after reset and must be disabled by software (when broadcast mode is used), if the device has no need to respond with data. 0 (Val_0x0): Slave output is enabled 1 (Val_0x1): Slave output is disabled |
| SRL | Shift Register Loop. Used for testing purposes only. When internally active, connects the transmit shift register output to the receive shift register input. Can be used in both serial slave and serial Master mode. When the SPI is configured as a slave in loopback mode, the slave select input and SPI_CLK signals must be provided by an external source. In this mode, the slave cannot generate these signals because there is nothing to which to loop back. 0 (Val_0x0): Normal Mode Operation 1 (Val_0x1): Test Mode Operation |
| SSTE | Slave Select Toggle Enable. While operating in SPI mode with clock phase (SCPH) set to 0x0, this bit controls the behavior of the slave select line between data frames. 0 (Val_0x0): The slave select line will stay low and SPI_SCLK will run continuously for the duration of the transfer 1 (Val_0x1): The slave select line will toggle between consecutive data frames, with the serial clock (SPI_SCLK) being held to its default value while the slave select line is high |
| CFS | Control Frame Size. Selects the length of the control word for the Microwire frame format. 0 (Val_0x0): 01-bit Control Word 1 (Val_0x1): 02-bit Control Word 2 (Val_0x2): 03-bit Control Word 3 (Val_0x3): 04-bit Control Word 4 (Val_0x4): 05-bit Control Word 5 (Val_0x5): 06-bit Control Word 6 (Val_0x6): 07-bit Control Word 7 (Val_0x7): 08-bit Control Word 8 (Val_0x8): 09-bit Control Word 9 (Val_0x9): 10-bit Control Word 10 (Val_0xA): 11-bit Control Word 11 (Val_0xB): 12-bit Control Word 12 (Val_0xC): 13-bit Control Word 13 (Val_0xD): 14-bit Control Word 14 (Val_0xE): 15-bit Control Word 15 (Val_0xF): 16-bit Control Word |
| SPI_IS_MST | This bit selects if the SPI is working in Master or Slave mode. 0 (Val_0x0): SPI is Slave 1 (Val_0x1): SPI is Master |